Pixel individual anti-eclipse circuit and its operation manner

ABSTRACT

An anti-eclipse circuit of an image pixel includes a pixel coupled to a pixel output line and a circuit for receiving and storing a pixel reset voltage from the pixel on the pixel output line and for using the stored pixel reset voltage as a parameter to control a reset voltage level on the output line in a manner which maintains the pixel reset voltage on the pixel output line above a predetermined minimum voltage.

FIELD OF INVENTION

The present invention relates generally to semiconductor imagers. Morespecifically, the present invention relates to an anti-eclipse circuitfor imagers.

BACKGROUND OF THE INVENTION

A CMOS imager circuit includes a focal plane array of pixel cells, eachone of the cells including a photosensor, for example, a photogate,photoconductor or a photodiode for accumulating photo-generated chargein a specified portion of a substrate. Each pixel cell has a chargestorage region, formed on or in the substrate, which is connected to thegate of an output transistor that is part of a readout circuit. Thecharge storage region may be constructed as a floating diffusion region.In some imager circuits, each pixel may include at least one electronicdevice such as a transistor for transferring charge from the photosensorto the storage region and one device, also typically a transistor, forresetting the storage region to a predetermined charge level prior tocharge transference.

In a CMOS imager, the active elements of a pixel cell perform thefunctions of: (1) photon to charge conversion; (2) accumulation of imagecharge; (3) resetting the storage region to a known state; (4) transferof charge to the storage region; (5) selection of a pixel for readout;and (6) output and amplification of a signal representing the charge atthe storage region. Photo-charge may be amplified when it moves from theinitial charge accumulation region to the storage region. The charge atthe storage region is typically converted to a pixel output voltage by asource follower output transistor.

CMOS imagers of the type discussed above are generally known asdiscussed, for example, in U.S. Pat. Nos. 6,140,630, 6,376,868,6,310,366, 6,326,652, 6,204,524 and 6,333,205, assigned to MicronTechnology, Inc., which are hereby incorporated by reference in theirentirety.

FIG. 1 is an illustration of a conventional four transistor (4T) pixel100 and an associated load circuit 120 (shown as a current source). Thepixel 100 includes a light sensitive element 101, shown as a photodiode,a floating diffusion region C, and four transistors: a transfertransistor 111, a reset transistor 112, a first source followertransistor 113, and a row select transistor 114. The pixel 100 accepts aTX control signal for controlling the conductivity of the transfertransistor 111, a RS control signal for controlling the conductivity ofthe reset transistor 112, and a SEL control signal for controlling theconductivity of the row select transistor 114. The charge at thefloating diffusion region C controls the conductivity of the firstsource follower transistor 113. The output of the source followtransistor 113 is presented to the load circuit 120 through the rowselect transistor 114, which outputs a pixel signal at node B, when therow select transistor 114 is conducting (i.e., when SEL is asserted).

The states of the transfer and reset transistors 111, 112 determinewhether the floating diffusion region C is coupled to the lightsensitive element 101 for receiving photo generated charge generated bythe light sensitive element 101 during a charge integration period, or asource of pixel power Vaapix from node A during a reset period.

The pixel 100 is operated as follows. The SEL control signal is assertedto cause the row select transistor 114 to conduct. At the same time, theRS control signal is asserted while the TX control signal is notasserted. This couples the floating diffusion region C to the pixelpower Vaapix at node A, and resets the voltage at node C to the aninitial voltage. The pixel 100 outputs a reset signal VRST to the loadcircuit 120. Node B is coupled between the row select transistor 114 andthe load circuit 120 and serves as an input to a sample and hold circuit(not shown )that samples and holds the pixel reset voltage VRST.

After the reset signal VRST has been output, the RS control signal isdeasserted. The light sensitive element 101 has been exposed to incidentlight and accumulates charge on the level of the incident light during acharge integration period. After the charge integration period and theoutput of the signal VRST, the TX control signal is asserted. Thiscouples the floating diffusion region C to the light sensitive element101. Charge flows through the transfer transistor 111 and diminishes thevoltage at the floating diffusion region C. The pixel 100 outputs aphoto signal VSIG to the load circuit 120 which appears at node B and issampled by the sample and hold circuit (not shown). The reset and photosignals VRST, VSIG are different components of the overall pixel output(i.e., Voutput=VRST−VSIG).

A pixel 100 is susceptible to a type of distortion known as eclipsing.Eclipsing refers to the distortion arising when a pixel outputs a pixelsignal corresponding to a dark pixel even though bright light isincident upon the pixel. Eclipsing can occur when a pixel is exposed tobright light, as the light sensitive element 101 can produce a largequantity of photogenerated charge. While the pixel 100 is outputting thereset signal VRST, a portion of the photogenerated charge produced bythe light sensitive element 101 during an ongoing integration period mayspill over the transfer transistor 111 into the floating diffusion nodeC. This diminishes the reset voltage at the floating diffusion node andcan causes the pixel 100 to output an incorrect (i.e., diminishedvoltage) reset signal VRST. This, in turn, can cause the reset and photosignals VRST, VSIG to be nearly the same voltage. For example, the photoand reset signals VRST, VSIG may each be approximately 0 volts. Thepixel output (VRST−VSIG) can therefore become approximately 0 volts,which corresponds to an output voltage normally associated with a darkpixel.

An anti-eclipse circuit can be used to minimize the effect of eclipsing.For example, since during an eclipse a pixel's reset voltage tends todrop towards zero volts, an anti-eclipse circuit can monitor the voltagelevel of the reset signal. If the voltage level drops below a thresholdvoltage, the anti-eclipse circuit can assume that the eclipsing mayoccur (or is occurring) and then correct the voltage level of the resetsignal by pulling the reset level up to a correction voltage, therebyminimizing the eclipse effect.

FIG. 2 is an illustration of the pixel 100, its load circuit 120, and aconventional anti-eclipse circuit 230 for overcoming the above-describedeclipse problem. The anti-eclipse circuit 230 comprises a second sourcefollower transistor 231 coupled in series with a switching transistor232. The output of the switching transistor 232 is coupled in parallelwith the output of the pixel 100 to the input of the load circuit 120(i.e., to node B). The second source follower transistor 231 has onesource/drain coupled to the pixel power Vaapix and another source/drainterminal coupled to the switching transistor 232. The second sourcefollower transistor 231 is biased with a VREF control signal. Theconductivity of the switching transistor 232 is controlled by a SHR(sample and hold reset) control signal which is used to sample and holdthe VRST signal. The VREF voltage level is set so that if the voltage onthe floating diffusion region C degrades while the reset signal VRST isbeing output, the second source follower transistor 231 conducts andpulls the voltage at node B up to VREF minus the threshold voltage ofthe second source follower transistor 231. One limitation of theanti-eclipse circuit 230 is to have a sufficient margin against possiblevariations of VRST. VRST is affected by threshold voltage variations ofboth reset transistor 112 and source follower transistor 113. Inaddition, temperature change, voltage change of VAA and a high level ofthe RS control pulse affect VRST. When anti-eclipsing is not needed, asin normal exposure conditions, current that flows through the secondsource follower transistor 231 should be zero in order to avoid anycontribution from the anti-eclipse circuit 230. Therefore, VREF shouldbe chosen as a sufficiently low voltage supposing a minimum value VRSTvariation, which results in reduced VREF voltage and causes difficultyin obtaining a sufficient output level for anti-eclipsing.

Accordingly, there is a need and desire for an improved anti-eclipsecircuit for imagers.

BRIEF SUMMARY OF THE INVENTION

Exemplary embodiments of the invention provide an anti-eclipse circuit,and method of forming the same, comprising a pixel coupled to a pixeloutput line and a circuit for receiving and storing a pixel resetvoltage from the pixel on the pixel output line and for using the storedpixel reset voltage as a parameter to control a reset voltage level onthe output line in a manner which maintains the pixel reset voltage onthe pixel output line above a predetermined minimum voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other advantages and features of the invention willbecome more apparent from the detailed description of exemplaryembodiments provided below with reference to the accompanying drawingsin which:

FIG. 1 illustrates a conventional pixel and an associated load circuit;

FIG. 2 illustrates a conventional pixel, a conventional load circuit,and conventional anti-eclipse circuit;

FIGS. 3A, 3B, and 3C illustrate a pixel, a load circuit, and ananti-eclipse circuit constructed in accordance with three exemplaryembodiments of the invention;

FIGS. 4A, 4B, and 4C are timing diagrams showing the signal timing andwaveform of the exemplary embodiments of the invention associated withthe FIGS. 3A, 3B, and 3C embodiments;

FIG. 5 is a block diagram of an imager, including an anti-eclipsecircuit in accordance with the invention; and

FIG. 6 illustrates a processing system incorporating the anti-eclipsecircuit of the invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, reference is made to theaccompanying drawings, which form a part hereof and show by way ofillustration specific embodiments in which the invention may bepracticed. These embodiments are described in sufficient detail toenable those skilled in the art to practice the invention, and it is tobe understood that other embodiments may be utilized, and thatstructural, logical, and electrical changes may be made withoutdeparting from the spirit and scope of the present invention. Theprogression of processing steps described is exemplary of embodiments ofthe invention; however, the sequence of steps is not limited to that setforth herein and may be changed as is known in the art, with theexception of steps necessarily occurring in a certain order.

The term “pixel,” as used herein, refers to a photo-element unit cellcontaining a photosensor and associated transistors for convertingphotons to an electrical signal. For purposes of illustration, a smallnumber of representative pixels are illustrated in the figures anddescription herein; however, typically fabrication of a large pluralityof like pixels proceeds simultaneously. Accordingly, the followingdetailed description is not to be taken in a limiting sense, and thescope of the present invention is defined only by the appended claims.

In addition, although the invention is described below with reference toa CMOS imager, the invention has applicability to any solid stateimaging device having a storage node which is reset and then has chargestransferred to it. The following detailed description is, therefore, notto be taken in a limiting sense, and the scope of the present inventionis defined only by the appended claims.

Now referring to the figures, where like numerals designate likeelements, FIG. 3A shows a first embodiment of the invention, whichincludes pixel circuit 100, a clip circuit 300, and a global multiplexcircuit 350. Pixel circuit 100 is the same as that described inconnection with FIG. 1. Clip circuit 300 includes a clip transistor 310,a clamp switch 320, a memory capacitor 330, and VSLICE_local node D.Global multiplex circuit 350 includes a first control switch 351, asecond control switch 352, and a third control switch 353. Clip circuit300 is connected to pixel 100 at node B. Clip transistor 310 isconnected at its drain to Vaapix (node A), and at its source is coupledto the first terminal of clamp switch 320 and thus to a column line ofan imager. The gate of clip transistor 310 is coupled to VSLICE_localnode D. The second terminal of clamp switch 320 is also connected tonode D. Memory capacitor 330 is coupled at one terminal to node D. Theother terminal of memory capacitor 330 is connected a common VSLICE bus340. Global multiplex circuit 350 drives the VSLICE bus 340 through thethree control switches 351, 352, and 353. The three switches enablevoltage output of signals VCL, VSLICE_R and VSLICE_S, respectively,where VSLICE_R>VCL>VSLICE_S. Load circuit 120 is represented as a loadtransistor 325 and signal VLN connected at the gate of load transistor325.

FIG. 4A describes an exemplary operation of the embodiment illustratedin FIG. 3A and also illustrates the reset voltage VRST level duringoperation of the FIG. 3A circuit. At time t0, row select signal SEL isapplied to the pixel 100 so that the pixel 100 is selected. Reset signalRS is pulsed and applied to reset transistor 112 at time t1. The voltageVpix at node C goes up to VDD (high level of the RS pulse)-VT-MRS, wheresaturation mode operation of reset transistor 112 is assumed and VT-MRSis a threshold voltage of reset transistor 112. The Vpix is set as theVpix initial voltage Vpix(rst). Pixel 100 outputs a reset signal VRSTaccording to the following equation, where MRD is a threshold voltage ofsource follower transistor 113.VRST=Vpix(rst)−V _(T-MRD)

Clamp switch 320 and switch 351 also close at time t1 when CL is pulsed.VRST is input at Vslice_local node D in the clip circuit 300. At timet2, CL is deasserted and clamp switch 320 turns off, and switch 352closes when SLICE_R is asserted high, so that the Vslice_local voltageat node D changes to,VSLICE_local(rst)=VRST+(VSLICE_(—) R−VCL)

where memory capacitor 330 is much larger than parasitic capacitance atnode D of Vslice_local so that ΔVSLICE˜ΔVSLICE_local. VSLICE_local(rst)is equivalent to VSLICE_R in the clip circuit and determines minimumlevel of Vpixout for reset duration and prevents the eclipse artifact.

The clip voltage for node B of Vpixout is then,Vclip(rst)=VRST+(VSLICE_(—) R−VCL)−V _(T) ₋ _MSL

where V_(T-MSL) is the threshold voltage of clip transistor 310.

Following VRST sampling to an external memory (not shown) when SHR isdeasserted at time t3, SLICE_R is deasserted so that switch 352 opensand SLICE_S is asserted so that switch 353 closes at time t4. ThenVSLICE_local and clip voltages change to,VSLICE_local(sig)=VRST+(VSLICE _(—) S−VCL)Vclip(sig)=VRST+(VSLICE_(—) S−VCL)−V _(T) ₋ _MSL.

At time t5 TX is asserted and transfer transistor 111 turns on and photogenerated charge accumulated at photodiode 101 is transferred fromphotodiode 101 to the floating diffusion node C, dropping Vpix thenVpixout as well. The Vpixout after the charge transfer is VSIG andsampled at another external memory (not shown) when sample and holdsignal SHS is asserted during time t5 and time t6. The voltage collectedby photosensor 101 can be obtained by subtracting VSIG from VRST. On theother hand, the clip voltage Vclip(sig) limits the minimum Vpixout inorder to avoid bias current cut-off when the pixel is in saturation.Clip voltages are based on reset voltage VRST that includes all VTvariations of threshold voltages of reset transistor 112 and sourcefollower transistor 113, VT-MRS and VT-MRD of a pixel. Therefore,variations of these threshold voltages no longer affect the necessarymargin for setting clip voltages and results in wider dynamic range. Inaddition, change over time of VRST due to temperature drift and/or powersupply change can also be ignored, so it accomplishes adjustment withoutsuch changes.

FIG. 3B illustrates a second embodiment of the invention. In comparisonwith FIG. 3A, a Vaapix enable transistor 360 is additionally implementedin clip circuit 300′. Vaapix enable switch 360 may be very small, as itis used to charge memory capacitor 330. Also, the location of clampswitch 320 is changed to the drain side of the clip transistor 310.

FIG. 4B describes the an exemplary operation of the embodimentillustrated in FIG. 3B and shows the resulting VRST signal duringcircuit operation. At time t0, row select signal SEL is applied to thepixel 100 so that the pixel 100 is selected. Reset signal RS is pulsedand charging signal SLICE_EN_BAR is deasserted at time t1. Since thesignal CL is pulsed, node D is connected with the Vaapix through Vaapixenable transistor 360 at this time. At time t1 a, charging signalSLICE_EN_BAR is asserted and the Vslice_local node D and drain node ofclip transistor 310 are both disconnected from Vaapix, so that theVslice_local voltage decreases with the charge that flows through cliptransistor 310. When Vpixout node B voltage decreases following decreaseof the Vslice_local voltage and reaches VRST, the clip circuit 300becomes inactive. When Vpixout will be clipped at VRST, the channelcurrent of clip transistor 310 is effectively cut-off and the voltage atVslice_local is set at VRST+VT-MSL. After the Vslice_local issufficiently stable, clamp switch 320 opens at time t2 and theVRST+VT-MSL is stored at the Vslice_local node D.

Following VRST sampling period, charging signal SLICE_EN_BAR turns offat time t2 a to enable the clip circuit after VSLICE bus 340 voltage ischanged from signal VCL to signal VSLICE_R at time t2. The clip levelfor the Vpixout node for the VRST sampling period is then,$\begin{matrix}{{{Vclip}\quad({rst})} = {{{Vslice\_ local}\quad({rst})} - V_{T\_ MSL}}} \\{= {{VRST} + V_{T\_ MSL} - \left( {{VCL} - {VSLICE\_ R}} \right) - V_{T\_ MSL}}} \\{= {{VRST} - \left( {{VCL} - {VSLICE\_ R}} \right)}}\end{matrix}$

and the VT_MSL no longer contributes the clip level. Also for the VSIGsampling period, clip level Vclip(sig) can be expressed as the followingequation and there is no contribution from VT_MSL as well during theVRST sampling period. $\begin{matrix}{{{Vclip}\quad({sig})} = {{{Vslice\_ local}\quad({sig})} - V_{T\_ MSL}}} \\{= {{VRST} + V_{T\_ MSL} - \left( {{VCL} - {VSLICE\_ S}} \right) - V_{T\_ MSL}}} \\{= {{VRST} - \left( {{VCL} - {VSLICE\_ S}} \right)}}\end{matrix}$

Accordingly, using a pulsed power supply method as explained above, thevariation of the VT_MSL can be cancelled, which improves the performanceof the clip circuit.

FIG. 3C shows a third embodiment of the invention. In comparison withthe configuration of the embodiment shown in FIG. 3B, a DC currentswitch 370 is introduced between clip transistor 310 and Vpixout node Bin clip circuit 300″. Second switch 370 is kept open when the drainvoltage of clip transistor 310 is driven to Vaapix, so that no DCcurrent flows during the charge up period of memory capacitor 330.

FIG. 4C describes the an exemplary operation of the embodimentillustrated in FIG. 3C. The operation is the same as that described inFIG. 4B, with an additional signal SLICE_EN2 that controls DC currentswitch 370. SLICE_EN2 is asserted at time t1 a at the same timeSLICE_EN_BAR is asserted, and SLICE_EN2 is deasserted at time t7 whenSLICE_EN_BAR in reasserted. This causes the voltage at node B to stay atVRST from time t1 to time t1 a to avoid affecting the sampled resetvoltage.

Each imager may also be arranged in an array, or as part of a processingsystem. Clip circuit 300 and global multiplexer circuit 350 would beconnected to each imager in the array at node B, which functions as acolumn line.

In FIG. 5, the CMOS imager 500 is operated by a control circuit 530,which controls address decoders 515, 525 for selecting the appropriaterow and column lines for pixel readout. Control circuit 530 alsocontrols the row and column driver circuitry 510, 520 so that they applydriving voltages to the drive transistors of the selected row and columnlines. The clip circuit 300 is implemented in each column. The pixeloutput signals typically include a pixel reset signal VRST read out ofthe storage region after it is reset by the reset transistor and a pixelimage signal VSIG, which is read out of the storage region afterphoto-generated charges are transferred to the region. The VRST and VSIGsignals are sampled by a sample and hold circuit 535 and are subtractedby a differential amplifier 540, to produce a differential signalVRST−VSIG for each pixel. VRST−VSIG represents the amount of lightimpinging on the pixels. This difference signal is digitized by ananalog-to-digital converter 545. The digitized pixel signals are fed toan image processor 550 to form a digital image output. The digitizingand image processing can be located on or off the imager chip. In somearrangements the differential signal VRST−VSIG can be amplified as adifferential signal and directly digitized by a differential analog todigital converter.

FIG. 6 illustrates a processor-based system 600, for example a camerasystem, which generally comprises a central processing unit (CPU) 605,such as a microprocessor, that communicates with an input/output (I/O)device 610 over a bus 615. The system 600 also includes an imagingdevice 500 constructed in accordance with any of the embodiments of theinvention. Imager 500 also communicates with the CPU 605 over bus 615.The processor-based system 600 also includes random access memory (RAM)620, and can include removable memory 625, such as flash memory, whichalso communicate with CPU 605 over the bus 615. Imager 500 may becombined with a processor, such as a CPU, digital signal processor, ormicroprocessor, with or without memory storage on a single integratedcircuit or on a different chip than the processor.

Various embodiments of the invention have been illustrated using aphotodiode as the charge conversion device, and in the environment of afour transistor pixel. It should be appreciated that, other types ofphotosensors and pixel architectures may be used to generate imagecharge. The invention may also be used in a readout circuit for a CCD(charge coupled device) array. Accordingly, it is not intended that thepresent invention be strictly limited to the above-described andillustrated embodiments. Any modifications of the present invention asdescribed in the embodiments herein that falls within the spirit andscope of the following claims should be considered part of the presentinvention.

1. An imager comprising: a pixel coupled to a pixel output line; and acircuit for receiving and storing a pixel reset voltage from said pixelon said pixel output line and for using said stored pixel reset voltageas a parameter to control a reset voltage level on said output line in amanner which maintains said pixel reset voltage on said pixel outputline above a predetermined minimum voltage.
 2. The imager of claim 1,wherein said circuit further comprises a voltage supply portion foradding a voltage to said stored reset voltage to produce a controlsignal.
 3. The imager of claim 1, wherein said circuit further comprisesa voltage controlling portion for controlling a voltage added to saidoutput line.
 4. The imager of claim 1, wherein said output line is acolumn line of a pixel array.
 5. The imager of claim 1, wherein saidcircuit further comprises a capacitor for storing said pixel resetvoltage.
 6. The imager of claim 1, wherein said circuit furthercomprises a voltage maintenance portion which adds a voltage to saidstored reset voltage sufficient to maintain a predetermined differencebetween an established minimum reset voltage level and said controlledreset voltage on said output line.
 7. The imager of claim 1, whereinsaid circuit comprises: a storage capacitor; a switch for selectivelycoupling said output line to said storage capacitor; a transistor forbiasing said output line to control the reset voltage level on saidline, a gate of said transistor being coupled to said storage capacitor;and a switchable voltage source for switchably applying an additionalvoltage to said capacitor.
 8. The imager of claim 7, wherein saidswitchable voltage source comprises: a plurality of voltage sourcelines; and a switch for selectively coupling a selected voltage sourceline to said capacitor.
 9. The imager of claim 8, wherein said outputline further receives a pixel output signal from said pixel and whereinsaid switch selectively couples a first voltage line having a firstvoltage higher than said predetermined minimum voltage to said capacitorbefore said output line receives said pixel output signal.
 10. Theimager of claim 7, wherein said transistor is coupled to a voltagesupply line and selectively controls application of a voltage from saidsupply line to said output line in response to voltage on saidcapacitor.
 11. The imager of claim 1, wherein said circuit comprises: astorage capacitor; a first transistor for selectively charging saidstorage capacitor; a switch for selectively coupling said firsttransistor to said storage capacitor; a second transistor for biasingsaid output line to control the reset voltage level on said line, a gateof said transistor being coupled to said storage capacitor; and aswitchable voltage source for switchably applying an additional voltageto said capacitor.
 12. The imager of claim 1, wherein said circuitcomprises: a storage capacitor; a first transistor for selectivelycharging said storage capacitor; a first switch for selectively couplingsaid first transistor to said storage capacitor; a second transistor forbiasing said output line to control the reset voltage level on saidline, a gate of said transistor being coupled to said storage capacitor;a second switch for avoiding a surge in current flow while said storagecapacitor is charging; and a switchable voltage source for switchablyapplying an additional voltage to said capacitor.
 13. A method ofoperating an imager comprising the steps of: receiving and storing apixel reset voltage from a pixel on an output line and for using saidstored pixel reset voltage as a parameter to control a reset voltagelevel on said output line in a manner which maintains said pixel resetvoltage on said pixel output line above a predetermined minimum voltage.14. The method of claim 13, further comprising the step of adding avoltage to said stored reset voltage to produce a control signal. 15.The method of claim 13, further comprising the step of controlling avoltage added to said output line.
 16. The method of claim 13, whereinsaid output line is a column line of a pixel array.
 17. The method ofclaim 13, further comprising the step of storing said pixel resetvoltage on a capacitor.
 18. The method of claim 13, further comprisingthe step of adding a voltage to said stored reset voltage sufficient tomaintain a predetermined difference between an established minimum resetvoltage level and said controlled reset voltage on said output line. 19.The method of claim 13, further comprising the steps of: selectivelycoupling said output line to a storage capacitor; biasing said outputline to control the reset voltage level on said line with a transistor,a gate of said transistor being coupled to said storage capacitor; andswitchably applying an additional voltage to said capacitor with aswitchable voltage source.
 20. The method of claim 19, furthercomprising the step of receiving a pixel output signal from said pixeland selectively coupling a first voltage line having a first voltagehigher than said predetermined minimum voltage to said capacitor beforesaid output line receives said pixel output signal.
 21. The method ofclaim 13, further comprising the steps of: selectively charging saidstorage capacitor with a first transistor; selectively coupling saidfirst transistor to said storage capacitor with a switch; biasing saidoutput line to control the reset voltage level with a second transistor,a gate of said transistor being coupled to said storage capacitor; andswitchably applying an additional voltage to said capacitor with aswitchable voltage source.
 22. The method of claim 13, furthercomprising the steps of: selectively charging said storage capacitorwith a first transistor; selectively coupling said first transistor tosaid storage capacitor with a switch; biasing said output line tocontrol the reset voltage level with a second transistor, a gate of saidtransistor being coupled to said storage capacitor; and avoiding a surgein current flow a second switch while said storage capacitor ischarging; and switchably applying an additional voltage to saidcapacitor with a switchable voltage source.
 23. An imager arraycomprising: a plurality of imager circuits, at least one imager circuitof said plurality comprising: a pixel coupled to a pixel output line;and a circuit for receiving and storing a pixel reset voltage from saidpixel on said pixel output line and for using said stored pixel resetvoltage as a parameter to control a reset voltage level on said outputline in a manner which maintains said pixel reset voltage on said pixeloutput line above a predetermined minimum voltage.
 24. The imager arrayof claim 23, wherein said circuit further comprises a voltage supplyportion for adding a voltage to said stored reset voltage to produce acontrol signal.
 25. The imager array of claim 23, wherein said circuitfurther comprises a voltage controlling portion for controlling avoltage added to said output line.
 26. The imager array of claim 23,wherein said output line is a column line of a pixel array.
 27. Theimager array of claim 23, wherein said circuit further comprises acapacitor for storing said pixel reset voltage.
 28. The imager array ofclaim 23, wherein said circuit further comprises a voltage maintenanceportion which adds a voltage to said stored reset voltage sufficient tomaintain a predetermined difference between an established minimum resetvoltage level and said controlled reset voltage on said output line. 29.The imager array of claim 23, wherein said circuit comprises: a storagecapacitor; a switch for selectively coupling said output line to saidstorage capacitor; a transistor for biasing said output line to controlthe reset voltage level on said line, a gate of said transistor beingcoupled to said storage capacitor; and a switchable voltage source forswitchably applying an additional voltage to said capacitor.
 30. Theimager array of claim 29, wherein said switchable voltage sourcecomprises: a plurality of voltage source lines; and a switch forselectively coupling a selected voltage source line to said capacitor.31. The imager array of claim 30, wherein said output line furtherreceives a pixel output signal from said pixel and wherein said switchselectively couples a first voltage line having a first voltage higherthan said predetermined minimum voltage to said capacitor before saidoutput line receives said pixel output signal.
 32. The imager array ofclaim 29, wherein said transistor is coupled to a voltage supply lineand selectively controls application of a voltage from said supply lineto said output line in response to voltage on said capacitor.
 33. Theimager array of claim 23, wherein said circuit comprises: a storagecapacitor; a first transistor for selectively charging said storagecapacitor; a switch for selectively coupling said first transistor tosaid storage capacitor; a second transistor for biasing said output lineto control the reset voltage level on said line, a gate of saidtransistor being coupled to said storage capacitor; and a switchablevoltage source for switchably applying an additional voltage to saidcapacitor.
 34. The imager array of claim 23, wherein said circuitcomprises: a storage capacitor; a first transistor for selectivelycharging said storage capacitor; a first switch for selectively couplingsaid first transistor to said storage capacitor; a second transistor forbiasing said output line to control the reset voltage level on saidline, a gate of said transistor being coupled to said storage capacitor;a second switch for avoiding a surge in current flow while said storagecapacitor is charging; and a switchable voltage source for switchablyapplying an additional voltage to said capacitor.
 35. A processingsystem comprising: a processor; and an imager array electronicallycoupled to said processor, said imager array comprising a plurality ofimager circuits, at least one imager circuit of said pluralitycomprising: a pixel coupled to a pixel output line; and a circuit forreceiving and storing a pixel reset voltage from said pixel on saidpixel output line and for using said stored pixel reset voltage as aparameter to control a reset voltage level on said output line in amanner which maintains said pixel reset voltage on said pixel outputline above a predetermined minimum voltage.
 36. The processing system ofclaim 35, wherein said circuit further comprises a voltage supplyportion for adding a voltage to said stored reset voltage to produce acontrol signal.
 37. The processing system of claim 35, wherein saidcircuit further comprises a voltage controlling portion for controllinga voltage added to said output line.
 38. The processing system of claim35, wherein said output line is a column line of a pixel array.
 39. Theprocessing system of claim 35, wherein said circuit further comprises acapacitor for storing said pixel reset voltage.
 40. The processingsystem of claim 35, wherein said circuit further comprises a voltagemaintenance portion which adds a voltage to said stored reset voltagesufficient to maintain a predetermined difference between an establishedminimum reset voltage level and said controlled reset voltage on saidoutput line.
 41. The processing system of claim 35, wherein said circuitcomprises: a storage capacitor; a switch for selectively coupling saidoutput line to said storage capacitor; a transistor for biasing saidoutput line to control the reset voltage level on said line, a gate ofsaid transistor being coupled to said storage capacitor; and aswitchable voltage source for switchably applying an additional voltageto said capacitor.
 42. The processing system of claim 41, wherein saidswitchable voltage source comprises: a plurality of voltage sourcelines; and a switch for selectively coupling a selected voltage sourceline to said capacitor.
 43. The processing system of claim 42, whereinsaid output line further receives a pixel output signal from said pixeland wherein said switch selectively couples a first voltage line havinga first voltage higher than said predetermined minimum voltage to saidcapacitor before said output line receives said pixel output signal. 44.The processing system of claim 41, wherein said transistor is coupled toa voltage supply line and selectively controls application of a voltagefrom said supply line to said output line in response to voltage on saidcapacitor.
 45. The processing system of claim 35, wherein said circuitcomprises: a storage capacitor; a first transistor for selectivelycharging said storage capacitor; a switch for selectively coupling saidfirst transistor to said storage capacitor; a second transistor forbiasing said output line to control the reset voltage level on saidline, a gate of said transistor being coupled to said storage capacitor;and a switchable voltage source for switchably applying an additionalvoltage to said capacitor.
 46. The processing system of claim 35,wherein said circuit comprises: a storage capacitor; a first transistorfor selectively charging said storage capacitor; a first switch forselectively coupling said first transistor to said storage capacitor; asecond transistor for biasing said output line to control the resetvoltage level on said line, a gate of said transistor being coupled tosaid storage capacitor; a second switch for avoiding a surge in currentflow while said storage capacitor is charging; and a switchable voltagesource for switchably applying an additional voltage to said capacitor.47. A method of forming an imager pixel comprising the steps of: forminga pixel coupled to a pixel output line; and forming a circuit forreceiving and storing a pixel reset voltage from said pixel on saidpixel output line and for using said stored pixel reset voltage as aparameter to control a reset voltage level on said output line in amanner which maintains said pixel reset voltage on said pixel outputline above a predetermined minimum voltage.
 48. The method of claim 47,wherein said step of forming a circuit further comprises forming avoltage supply portion for adding a voltage to said stored reset voltageto produce a control signal.
 49. The method of claim 47, wherein saidstep of forming a circuit further comprises forming a voltagecontrolling portion for controlling a voltage added to said output line.50. The method of claim 47, wherein said step of forming the circuitfurther comprises forming said output line as a column line of a pixelarray.
 51. The method of claim 47, wherein said step of forming thecircuit further comprises forming a capacitor for storing said pixelreset voltage.
 52. The method of claim 47, wherein said step of formingthe circuit further comprises forming a voltage maintenance portionwhich adds a voltage to said stored reset voltage sufficient to maintaina predetermined difference between an established minimum reset voltagelevel and said controlled reset voltage on said output line.
 53. Themethod of claim 47, wherein said step of forming the circuit furthercomprises: forming a storage capacitor; forming a switch for selectivelycoupling said output line to said storage capacitor; forming atransistor for biasing said output line to control a reset voltage levelon said line, a gate of said transistor being coupled to said storagecapacitor; and forming a switchable voltage source for switchablyapplying an additional voltage to said capacitor.
 54. The method ofclaim 53, wherein said step of forming the switchable voltage sourcecomprises: forming a plurality of voltage source lines; and forming aswitch for selectively coupling a selected voltage source line to saidcapacitor.
 55. The method of claim 54, wherein said output line isformed to receive a pixel output signal from said pixel and wherein saidswitch is formed to selectively couple a first voltage line having afirst voltage higher than said predetermined minimum voltage to saidcapacitor before said output line receives said pixel output signal. 56.The method of claim 53, wherein said step of forming the transistorfurther comprises forming said transistor to be coupled to a voltagesupply line and to selectively control application of a voltage fromsaid supply line to said output line in response to voltage on saidcapacitor.
 57. The method of claim 47, wherein said step of forming thecircuit further comprises: forming a storage capacitor; forming a firsttransistor for selectively charging said storage capacitor; forming aswitch for selectively coupling said first transistor to said storagecapacitor; forming a second transistor for biasing said output line tocontrol a reset voltage level on said line, a gate of said transistorbeing coupled to said storage capacitor; and forming a switchablevoltage source for switchably applying an additional voltage to saidcapacitor.
 58. The method of claim 47, wherein said step of forming thecircuit further comprises: forming a storage capacitor; forming a firsttransistor for selectively charging said storage capacitor; forming afirst switch for selectively coupling said first transistor to saidstorage capacitor; forming a second transistor for biasing said outputline to control a reset voltage level on said line, a gate of saidtransistor being coupled to said storage capacitor; forming a secondswitch for avoiding a surge in current flow while said storage capacitoris charging; and forming a switchable voltage source for switchablyapplying an additional voltage to said capacitor.
 59. An imagercomprising: a pixel for supplying a pixel reset voltage; and a circuitfor monitoring said pixel reset voltage and for producing in response tosaid monitored pixel reset voltage a voltage on the line which has awaveform which starts at a nominal voltage, then increases to maintain adifferential above a predetermined minimum voltage until an output ofsaid pixel is read out.
 60. A method of operating an imager comprising:supplying a pixel reset voltage; and monitoring said pixel reset voltageand producing in response to said monitored pixel reset voltage avoltage on the line which has a waveform which starts at a nominalvoltage, then increases to maintain a differential above a predeterminedminimum voltage until an output is read out.